The present invention relates to semiconductor integrated circuit devices and methods for manufacturing the same and, more particularly, to a technique effectively used for semiconductor integrated circuit devices having a static memory (SRAM; static random access memory) and logic circuits.
AN-SRAM is a memory device utilizing a flip-flop circuit as a memory element, the bi-stable states of which are respectively stored in association with xe2x80x9c1xe2x80x9d and xe2x80x9cOxe2x80x9d levels of information, and it is characterized in that it is easy to use because it requires no refresh operation, unlike a DRAM (dynamic random access memory). The flip-flop circuit is formed by two inverter circuits. The output of one of the inverter circuits is electrically connected to the input of the other inverter circuit, and the output of the other inverter circuit is electrically connected to the input of the first inverter circuit. Each of the inverter circuits includes a driving transistor that contributes to the storage of information and a load element for supplying a power supply voltage to the driving transistor. Further, the flip-flop circuit is provided between a pair of data lines, and a structure is employed in which a transfer transistor is interposed between the flip-flop circuit and each of the data lines to electrically connect or electrically disconnect the flip-flop circuit and the data lines.
Memory cells for such an SRAM are categorized into high resistance load type cells and CMIS (complementary metal insulator semiconductor) type cells depending on the load elements in the memory cells. In the high resistance load type, a polysilicon resistor is used as a load element. In this case, since the resistor occupies a small area and can be overlaid on a driving transistor or the like, the total area of a memory cell region can be minimized to provide a large capacity. On the other hand, a p-channel type MISFET is used as a load element in the CMIS type, which minimizes the power consumption of the same. Some CMIS type memory cells have a so-called TFT (thin film transistor) structure in which two polysilicon layers are provided on a layer above of an n-channel type MOSFET serving as a driving transistor and in which a p-channel type MOSFET to be used as a load element is formed by the polysilicon layers to also reduce the total area of the memory cell region.
For example, a semiconductor integrated circuit device having an SRAM is described in Japanese Patent Laid-Open No. 167655/1996. In order to integrate high performance logic circuits and a highly integrated CMOS type memory cell array in the same chip without increasing the complexity of the manufacturing processes, a structure is disclosed in which logic circuits are formed by a top channel type n-channel MOSFET and p-channel MOSFET and in which a memory cell is formed by directly connecting the gate electrodes of the n-channel MOSFET and p-channel MOSFET having the same conductivity.
International Publication No. W97/38444 discloses an adjustment on the threshold voltage of a transfer transistor of an SRAM.
The inventor has found that the above-described technique for semiconductor integrated circuit devices having an SRAM has the following problems.
Specifically, semiconductor integrated circuit devices having an SRAM have had a problem in that no sufficient attention has been paid to the need for setting separate threshold voltages for elements forming memory cells and other elements that arises from the trend toward higher speeds, lower power consumption and higher integration of elements and in that semiconductor integrated circuit devices have operational faults in the memory circuit which have not been revealed in the past when they are manufactured giving consideration only to ease of manufacture. For example, semiconductor integrated circuit devices having an SRAM and logic circuits provided on the same semiconductor substrate have been subjected to increasing efforts toward logic circuits and SRAM peripheral circuits (hereinafter referred to xe2x80x9clogic circuits and the likexe2x80x9d) having higher speeds and toward lower power consumption and higher integration of the semiconductor integrated circuit devices as a whole. Efforts are being made to decrease the threshold voltage of the logic circuits and the like in order to increase the speed of the same. However, when the threshold voltages of a logic circuit and the like and a memory circuit are set at the same step taking only factors such as ease of manufacture into consideration without considering the significant trend toward increased speed of a logic circuit and the like and lower power consumption of a semiconductor integrated circuit device, the noise margin of memory cells in the memory circuit is reduced although the operating speed of the logic circuit and the like can be improved. Studies made by the inventors have revealed that this causes operational faults of the memory circuit which have not occurred even with the threshold voltages of the logical circuit and the like and the memory circuit set at the same step.
It is an object of the invention to provide a technique which makes it possible to improve the operational margin of a memory of a semiconductor-integrated circuit device having an SRAM.
It is another object of the invention to provide a technique which makes it possible to reduce the power consumption of a semiconductor integrated circuit device having an SRAM.
It is an object of the invention to provide a technique which makes it possible to improve the margin of writing to a memory of a semiconductor integrated circuit device having an SRAM.
The above and other objects and novel features of the invention will be apparent from the description provided in this specification and the accompanying drawings.
Typical aspects of the invention disclosed in this specification can be briefly described as follows.
A semiconductor integrated circuit device according to the invention has a plurality of first field effect transistors forming a memory cell of an SRAM and a second field effect transistor provided on a semiconductor substrate, in which the threshold voltage of at least one first field effect transistor among said plurality of first field effect transistors is relatively higher than the threshold voltage of said second field effect transistor.
A method of manufacturing a semiconductor integrated circuit device according to the invention, and having a plurality of first field effect transistors forming a memory cell of an SRAM and a second field effect transistor formed on a semiconductor substrate, includes an impurity introduction step for selectively introducing a first impurity into a region to form at least one of said first field effect transistors on said semiconductor substrate in order to set the threshold voltage of said at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor.
A method of manufacturing a semiconductor integrated circuit device according to the invention, and having a plurality of first field effect transistors forming a memory cell of an SRAM and a second field effect transistor formed on a semiconductor substrate, includes a step of selectively introducing nitrogen into the region to form said second field effect transistor on said semiconductor substrate and thereafter forming a gate insulation film on said semiconductor substrate in order to set the threshold voltage of said at least one first field effect transistor among said plurality of first field effect transistors relatively higher than the threshold voltage of said second field effect transistor.